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https://github.com/openbsd/ports.git
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emulators/qemu: backport i386 fix and add OpenBSD/powerpc64 support
OK: Brad Smith <brad@comstyle.com> (maintainer)
This commit is contained in:
kirill
@@ -7,6 +7,7 @@ COMMENT-main= multi system emulator
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COMMENT-ga= QEMU guest agent
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COMMENT-ga= QEMU guest agent
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VERSION= 11.0.1
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VERSION= 11.0.1
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REVISION-main= 0
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DISTNAME= qemu-${VERSION}
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DISTNAME= qemu-${VERSION}
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CATEGORIES= emulators
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CATEGORIES= emulators
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SITES= https://download.qemu.org/
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SITES= https://download.qemu.org/
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@@ -39,6 +40,7 @@ MODPY_RUNDEP= No
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BUILD_DEPENDS= devel/gettext,-tools \
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BUILD_DEPENDS= devel/gettext,-tools \
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devel/meson \
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devel/meson \
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devel/ninja \
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devel/ninja \
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devel/py-setuptools \
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shells/bash \
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shells/bash \
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sysutils/py-distlib \
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sysutils/py-distlib \
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textproc/py-sphinx \
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textproc/py-sphinx \
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@@ -0,0 +1,39 @@
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https://marc.info/?l=qemu-devel&m=178097910779871&w=2
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Index: hw/ppc/pnv_psi.c
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--- hw/ppc/pnv_psi.c.orig
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+++ hw/ppc/pnv_psi.c
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@@ -688,6 +688,8 @@ static uint64_t pnv_psi_p9_mmio_read(void *opaque, hwa
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case PSIHB9_ESB_CI_BASE:
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case PSIHB9_ESB_NOTIF_ADDR:
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case PSIHB9_IVT_OFFSET:
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+ case PSIHB9_IRQ_LEVEL:
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+ case PSIHB9_IRQ_STAT:
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val = psi->regs[reg];
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break;
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default:
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@@ -817,18 +819,15 @@ static const MemoryRegionOps pnv_psi_p9_xscom_ops = {
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static void pnv_psi_power9_set_irq(void *opaque, int irq, int state)
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{
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PnvPsi *psi = opaque;
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- uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)];
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+ uint64_t irq_bit = PPC_BIT(irq);
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- if (irq_method & PSIHB9_IRQ_METHOD) {
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- qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n");
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- return;
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- }
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-
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- /* Update LSI levels */
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+ /* Update LSI levels and pending status */
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if (state) {
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- psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq);
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+ psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= irq_bit;
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+ psi->regs[PSIHB_REG(PSIHB9_IRQ_STAT)] |= irq_bit;
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} else {
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- psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq);
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+ psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~irq_bit;
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+ psi->regs[PSIHB_REG(PSIHB9_IRQ_STAT)] &= ~irq_bit;
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}
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qemu_set_irq(psi->qirqs[irq], state);
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@@ -0,0 +1,22 @@
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https://marc.info/?l=qemu-devel&m=178096490372293&w=2
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Index: target/i386/tcg/emit.c.inc
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--- target/i386/tcg/emit.c.inc.orig
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+++ target/i386/tcg/emit.c.inc
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@@ -3768,10 +3768,13 @@ static void gen_SAHF(DisasContext *s, X86DecodedInsn *
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return gen_illegal_opcode(s);
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}
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tcg_gen_shri_tl(s->T0, cpu_regs[R_EAX], 8);
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- gen_neg_setcc(s, JCC_O << 1, cpu_cc_src);
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- tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
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+ gen_neg_setcc(s, JCC_O << 1, s->T1);
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+ tcg_gen_andi_tl(s->T1, s->T1, CC_O);
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tcg_gen_andi_tl(s->T0, s->T0, CC_S | CC_Z | CC_A | CC_P | CC_C);
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- tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, s->T0);
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+ tcg_gen_or_tl(s->T0, s->T0, s->T1);
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+
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+ decode->cc_src = s->T0;
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+ decode->cc_op = CC_OP_EFLAGS;
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}
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static void gen_SALC(DisasContext *s, X86DecodedInsn *decode)
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@@ -0,0 +1,58 @@
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https://marc.info/?l=qemu-devel&m=178097910779871&w=2
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Index: target/ppc/mmu-book3s-v3.c
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--- target/ppc/mmu-book3s-v3.c.orig
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+++ target/ppc/mmu-book3s-v3.c
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@@ -23,19 +23,21 @@
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#include "mmu-hash64.h"
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#include "mmu-book3s-v3.h"
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-bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t *entry)
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+static bool ppc64_v3_get_pate_from_size(PowerPCCPU *cpu, target_ulong lpid,
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+ ppc_v3_pate_t *entry,
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+ uint64_t table_size)
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{
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uint64_t patb = cpu->env.spr[SPR_PTCR] & PTCR_PATB;
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- uint64_t pats = cpu->env.spr[SPR_PTCR] & PTCR_PATS;
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+ uint64_t entries;
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/* Check if partition table is properly aligned */
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- if (patb & MAKE_64BIT_MASK(0, pats + 12)) {
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+ if (patb & (table_size - 1)) {
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return false;
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}
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/* Calculate number of entries */
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- pats = 1ull << (pats + 12 - 4);
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- if (pats <= lpid) {
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+ entries = table_size / sizeof(*entry);
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+ if (entries <= lpid) {
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return false;
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}
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@@ -44,4 +46,25 @@ bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong l
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entry->dw0 = ldq_phys(CPU(cpu)->as, patb);
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entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8);
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return true;
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+}
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+
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+bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t *entry)
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+{
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+ uint64_t pats = cpu->env.spr[SPR_PTCR] & PTCR_PATS;
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+
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+ /*
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+ * Keep the existing ISA v3.0 PATS interpretation first. OpenBSD/powernv
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+ * uses the PATSIZE value it writes to PTCR as one exponent smaller, and it
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+ * only needs that interpretation for the bare metal LPID 0 table.
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+ */
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+ if (ppc64_v3_get_pate_from_size(cpu, lpid, entry, 1ull << (pats + 12))) {
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+ return true;
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+ }
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+
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+ if (lpid == 0) {
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+ return ppc64_v3_get_pate_from_size(cpu, lpid, entry,
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+ 1ull << (pats + 11));
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+ }
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+
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+ return false;
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}
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