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update to 22.1.7

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This commit is contained in:
robert
2026-06-02 13:16:58 +00:00
parent 11a789d7a1
commit 72ba2bc645
5 changed files with 13 additions and 46 deletions
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devel/llvm/22/Makefile
+1 -3
View File
@@ -2,11 +2,9 @@
ONLY_FOR_ARCHS = amd64 arm64
LLVM_MAJOR = 22
LLVM_VERSION = ${LLVM_MAJOR}.1.6
LLVM_VERSION = ${LLVM_MAJOR}.1.7
LLVM_PKGSPEC = >=22,<23
REVISION-main = 0
SHARED_LIBS += LLVM 0.0 \
LTO 0.0 \
Remarks 0.0 \
devel/llvm/22/distinfo
+2 -2
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@@ -1,2 +1,2 @@
SHA256 (llvm-project-22.1.6.src.tar.xz) = bgs3ah9tmHPn37Ca5uBLnHAkQA8Bcz+kwpvmnVwTi8I=
SIZE (llvm-project-22.1.6.src.tar.xz) = 167043464
SHA256 (llvm-project-22.1.7.src.tar.xz) = XMSj8Su6ULa9+0thvchSEXoP8lF4B8OQL8EyZ/uTVi4=
SIZE (llvm-project-22.1.7.src.tar.xz) = 167066344
devel/llvm/22/patches/patch-lld_ELF_InputFiles_cpp
+2 -2
View File
@@ -43,7 +43,7 @@ Index: lld/ELF/InputFiles.cpp
break;
case SHT_LLVM_LTO:
// Discard .llvm.lto in a relocatable link that does not use the bitcode.
@@ -1567,6 +1588,9 @@ template <class ELFT> void SharedFile::parse() {
@@ -1565,6 +1586,9 @@ template <class ELFT> void SharedFile::parse() {
const ELFFile<ELFT> obj = this->getObj<ELFT>();
ArrayRef<Elf_Shdr> sections = getELFShdrs<ELFT>();
@@ -53,7 +53,7 @@ Index: lld/ELF/InputFiles.cpp
const Elf_Shdr *versymSec = nullptr;
const Elf_Shdr *verdefSec = nullptr;
const Elf_Shdr *verneedSec = nullptr;
@@ -1590,6 +1614,13 @@ template <class ELFT> void SharedFile::parse() {
@@ -1588,6 +1612,13 @@ template <class ELFT> void SharedFile::parse() {
case SHT_GNU_verneed:
verneedSec = &sec;
break;
devel/llvm/22/patches/patch-lld_ELF_Symbols_h
+8 -8
View File
@@ -11,16 +11,16 @@ Index: lld/ELF/Symbols.h
// Symbol visibility. This is the computed minimum visibility of all
// observed non-DSO symbols.
uint8_t visibility() const { return stOther & 3; }
@@ -243,7 +246,7 @@ class Symbol { (public)
uint8_t stOther, uint8_t type)
: file(file), nameData(name.data()), nameSize(name.size()), type(type),
binding(binding), stOther(stOther), symbolKind(k), ltoCanOmit(false),
- archSpecificBit(false) {}
+ gwarn(false), archSpecificBit(false) {}
@@ -247,7 +250,7 @@ class Symbol { (public)
traced(false), hasVersionSuffix(false), isInIplt(false),
gotInIgot(false), folded(false), archSpecificBit(false),
scriptDefined(false), dsoDefined(false), dsoProtected(false),
- versionScriptAssigned(false), thunkAccessed(false),
+ versionScriptAssigned(false), thunkAccessed(false), gwarn(false),
inDynamicList(false), referenced(false), referencedAfterWrap(false) {}
void overwrite(Symbol &sym, Kind k) const {
if (sym.traced)
@@ -536,6 +539,8 @@ void reportDuplicate(Ctx &, const Symbol &sym, const I
@@ -540,6 +543,8 @@ void reportDuplicate(Ctx &, const Symbol &sym, const I
void maybeWarnUnorderableSymbol(Ctx &, const Symbol *sym);
bool computeIsPreemptible(Ctx &, const Symbol &sym);
void parseVersionAndComputeIsPreemptible(Ctx &);
devel/llvm/22/patches/patch-llvm_lib_Target_X86_X86ISelLowering_cpp
-31
View File
@@ -1,31 +0,0 @@
Backport https://github.com/llvm/llvm-project/commit/1b9fea021840f17c41ea980300d0fc45e7285909
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
--- llvm/lib/Target/X86/X86ISelLowering.cpp.orig
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -18004,9 +18004,12 @@ static SDValue lowerV64I8Shuffle(const SDLoc &DL, Arra
// Try to create an in-lane repeating shuffle mask and then shuffle the
// results into the target lanes.
- if (SDValue V = lowerShuffleAsRepeatedMaskAndLanePermute(
- DL, MVT::v64i8, V1, V2, Mask, Subtarget, DAG))
- return V;
+ // FIXME: Avoid on VBMI targets as the post lane permute often interferes
+ // with shuffle combining (should be fixed by topological DAG sorting).
+ if (!Subtarget.hasVBMI())
+ if (SDValue V = lowerShuffleAsRepeatedMaskAndLanePermute(
+ DL, MVT::v64i8, V1, V2, Mask, Subtarget, DAG))
+ return V;
if (SDValue Result = lowerShuffleAsLanePermuteAndPermute(
DL, MVT::v64i8, V1, V2, Mask, DAG, Subtarget))
@@ -18041,7 +18044,8 @@ static SDValue lowerV64I8Shuffle(const SDLoc &DL, Arra
if (Subtarget.hasVBMI())
return lowerShuffleWithPERMV(DL, MVT::v64i8, Mask, V1, V2, Subtarget, DAG);
- return splitAndLowerShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG, /*SimpleOnly*/ false);
+ return splitAndLowerShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG,
+ /*SimpleOnly*/ false);
}
/// High-level routine to lower various 512-bit x86 vector shuffles.