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Implememnt mwx_reg_addr() for both 7921 and 7925
Also implement the L1 reg access for 7921 and 7925. Based on a diff from kevlo@
This commit is contained in:
claudio
+157
-77
@@ -1,4 +1,4 @@
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/* $OpenBSD: if_mwx.c,v 1.17 2026/06/02 13:20:28 claudio Exp $ */
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/* $OpenBSD: if_mwx.c,v 1.18 2026/06/02 14:23:47 claudio Exp $ */
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/*
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* Copyright (c) 2022 Claudio Jeker <claudio@openbsd.org>
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* Copyright (c) 2021 MediaTek Inc.
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@@ -70,6 +70,113 @@ static const struct pci_matchid mwx_devices[] = {
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#define MT7925_ROM_PATCH "mwx-mt7925_patch_mcu_1_1_hdr"
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#define MT7925_FIRMWARE_WM "mwx-mt7925_ram_code_1_1"
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struct mwx_connac_reg_map {
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uint32_t phys;
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uint32_t maps;
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uint32_t size;
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};
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static const struct mwx_connac_reg_map mt7921_fixed_map[] = {
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{ 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
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{ 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
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{ 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
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{ 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
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{ 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
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{ 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
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{ 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
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{ 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
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{ 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
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{ 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (conf register) */
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{ 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
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{ 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */
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{ 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */
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{ 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
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{ 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */
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{ 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
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{ 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
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{ 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
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{ 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
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{ 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
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{ 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
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{ 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
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{ 0x820cc000, 0x0e000, 0x01000 }, /* WF_UMAC_TOP (PP) */
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{ 0x820cd000, 0x0f000, 0x01000 }, /* WF_MDP_TOP */
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{ 0x74030000, 0x10000, 0x10000 }, /* PCIE_MAC_IREG */
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{ 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
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{ 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
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{ 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
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{ 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
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{ 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
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{ 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
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{ 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
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{ 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
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{ 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
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{ 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
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{ 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
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{ 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
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{ 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
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{ 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
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{ 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
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{ 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
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{ 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
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{ 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
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{ 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
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};
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static const struct mwx_connac_reg_map mt7925_fixed_map[] = {
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{ 0x830c0000, 0x000000, 0x0001000 }, /* WF_MCU_BUS_CR_REMAP */
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{ 0x54000000, 0x002000, 0x0001000 }, /* WFDMA PCIE0 MCU DMA0 */
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{ 0x55000000, 0x003000, 0x0001000 }, /* WFDMA PCIE0 MCU DMA1 */
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{ 0x56000000, 0x004000, 0x0001000 }, /* WFDMA reserved */
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{ 0x57000000, 0x005000, 0x0001000 }, /* WFDMA MCU wrap CR */
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{ 0x58000000, 0x006000, 0x0001000 }, /* WFDMA PCIE1 MCU DMA0 */
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{ 0x59000000, 0x007000, 0x0001000 }, /* WFDMA PCIE1 MCU DMA1 */
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{ 0x820c0000, 0x008000, 0x0004000 }, /* WF_UMAC_TOP (PLE) */
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{ 0x820c8000, 0x00c000, 0x0002000 }, /* WF_UMAC_TOP (PSE) */
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{ 0x820cc000, 0x00e000, 0x0002000 }, /* WF_UMAC_TOP (PP) */
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{ 0x74030000, 0x010000, 0x0001000 }, /* PCIe MAC */
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{ 0x820e0000, 0x020000, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
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{ 0x820e1000, 0x020400, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
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{ 0x820e2000, 0x020800, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
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{ 0x820e3000, 0x020c00, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
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{ 0x820e4000, 0x021000, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
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{ 0x820e5000, 0x021400, 0x0000800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
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{ 0x820ce000, 0x021c00, 0x0000200 }, /* WF_LMAC_TOP (WF_SEC) */
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{ 0x820e7000, 0x021e00, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
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{ 0x820cf000, 0x022000, 0x0001000 }, /* WF_LMAC_TOP (WF_PF) */
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{ 0x820e9000, 0x023400, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
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{ 0x820ea000, 0x024000, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
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{ 0x820eb000, 0x024200, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
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{ 0x820ec000, 0x024600, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
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{ 0x820ed000, 0x024800, 0x0000800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
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{ 0x820ca000, 0x026000, 0x0002000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
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{ 0x820d0000, 0x030000, 0x0010000 }, /* WF_LMAC_TOP (WF_WTBLON) */
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{ 0x40000000, 0x070000, 0x0010000 }, /* WF_UMAC_SYSRAM */
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{ 0x00400000, 0x080000, 0x0010000 }, /* WF_MCU_SYSRAM */
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{ 0x00410000, 0x090000, 0x0010000 }, /* WF_MCU_SYSRAM (config reg) */
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{ 0x820f0000, 0x0a0000, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
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{ 0x820f1000, 0x0a0600, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
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{ 0x820f2000, 0x0a0800, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
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{ 0x820f3000, 0x0a0c00, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
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{ 0x820f4000, 0x0a1000, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
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{ 0x820f5000, 0x0a1400, 0x0000800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
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{ 0x820f7000, 0x0a1e00, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
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{ 0x820f9000, 0x0a3400, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
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{ 0x820fa000, 0x0a4000, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
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{ 0x820fb000, 0x0a4200, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
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{ 0x820fc000, 0x0a4600, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
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{ 0x820fd000, 0x0a4800, 0x0000800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
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{ 0x820c4000, 0x0a8000, 0x0004000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
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{ 0x820b0000, 0x0ae000, 0x0001000 }, /* [APB2] WFSYS_ON */
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{ 0x80020000, 0x0b0000, 0x0010000 }, /* WF_TOP_MISC_OFF */
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{ 0x81020000, 0x0c0000, 0x0010000 }, /* WF_TOP_MISC_ON */
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{ 0x7c020000, 0x0d0000, 0x0010000 }, /* CONN_INFRA, wfdma */
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{ 0x7c060000, 0x0e0000, 0x0010000 }, /* CONN_INFRA, conn_host_csr_top */
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{ 0x7c000000, 0x0f0000, 0x0010000 }, /* CONN_INFRA */
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{ 0x70020000, 0x1f0000, 0x0010000 }, /* Reserved for CBTOP */
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{ 0x7c500000, 0x060000, 0x2000000 }, /* remap */
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};
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#if NBPFILTER > 0
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struct mwx_rx_radiotap_header {
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struct ieee80211_radiotap_header wr_ihdr;
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@@ -294,7 +401,6 @@ const struct mwx_rate {
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{ 108, (MT_PHY_TYPE_OFDM << 8) | 12 },
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};
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#define MWX_NUM_6GHZ_CHANNELS nitems(mwx_channels_6ghz)
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#define DEVNAME(s) ((s)->sc_dev.dv_xname)
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@@ -403,7 +509,7 @@ void mt7921_dma_enable(struct mwx_softc *sc);
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int mwx_mcu_fw_pmctrl(struct mwx_softc *);
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int mwx_mcu_drv_pmctrl(struct mwx_softc *);
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int mwx_wfsys_reset(struct mwx_softc *sc);
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uint32_t mt7921_reg_addr(struct mwx_softc *, uint32_t);
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uint32_t mwx_reg_addr(struct mwx_softc *, uint32_t);
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int mt7921_init_hardware(struct mwx_softc *);
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int mt7921_mcu_init(struct mwx_softc *);
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int mt7921_load_firmware(struct mwx_softc *);
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@@ -476,14 +582,14 @@ int mt7921_mac_sta_update(struct mwx_softc *,
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static inline uint32_t
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mwx_read(struct mwx_softc *sc, uint32_t reg)
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{
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reg = mt7921_reg_addr(sc, reg);
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reg = mwx_reg_addr(sc, reg);
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return bus_space_read_4(sc->sc_st, sc->sc_memh, reg);
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}
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static inline void
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mwx_write(struct mwx_softc *sc, uint32_t reg, uint32_t val)
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{
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reg = mt7921_reg_addr(sc, reg);
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reg = mwx_reg_addr(sc, reg);
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bus_space_write_4(sc->sc_st, sc->sc_memh, reg, val);
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}
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@@ -497,7 +603,7 @@ mwx_barrier(struct mwx_softc *sc)
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static inline uint32_t
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mwx_rmw(struct mwx_softc *sc, uint32_t reg, uint32_t val, uint32_t mask)
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{
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reg = mt7921_reg_addr(sc, reg);
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reg = mwx_reg_addr(sc, reg);
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val |= bus_space_read_4(sc->sc_st, sc->sc_memh, reg) & ~mask;
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bus_space_write_4(sc->sc_st, sc->sc_memh, reg, val);
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return val;
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@@ -516,15 +622,27 @@ mwx_clear(struct mwx_softc *sc, uint32_t reg, uint32_t bits)
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}
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static inline uint32_t
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mwx_map_reg_l1(struct mwx_softc *sc, uint32_t reg)
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mt7921_map_reg_l1(struct mwx_softc *sc, uint32_t reg)
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{
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uint32_t offset = MT_HIF_REMAP_L1_GET_OFFSET(reg);
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uint32_t base = MT_HIF_REMAP_L1_GET_BASE(reg);
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uint32_t offset = MWX_HIF_REG_OFFSET(reg);
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uint32_t base = MWX_HIF_REG_BASE(reg) << MT7921_HIF_REMAP_L1_SHIFT;
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mwx_rmw(sc, MT_HIF_REMAP_L1, base, MT_HIF_REMAP_L1_MASK);
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mwx_rmw(sc, MT7921_HIF_REMAP_L1, base, MT7921_HIF_REMAP_L1_MASK);
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mwx_barrier(sc);
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return MT_HIF_REMAP_BASE_L1 + offset;
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return MT7921_HIF_REMAP_BASE_L1 + offset;
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}
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static inline uint32_t
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mt7925_map_reg_l1(struct mwx_softc *sc, uint32_t reg)
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{
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uint32_t offset = MWX_HIF_REG_OFFSET(reg);
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uint32_t base = MWX_HIF_REG_BASE(reg) << MT7925_HIF_REMAP_L1_SHIFT;
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mwx_rmw(sc, MT7925_HIF_REMAP_L1, base, MT7925_HIF_REMAP_L1_MASK);
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mwx_barrier(sc);
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return MT7925_HIF_REMAP_BASE_L1 + offset;
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}
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/*
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@@ -538,7 +656,7 @@ mwx_poll(struct mwx_softc *sc, uint32_t reg, uint32_t val, uint32_t mask,
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{
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uint32_t cur;
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reg = mt7921_reg_addr(sc, reg);
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reg = mwx_reg_addr(sc, reg);
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timeout *= 100;
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do {
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cur = bus_space_read_4(sc->sc_st, sc->sc_memh, reg) & mask;
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@@ -2702,83 +2820,45 @@ mwx_wfsys_reset(struct mwx_softc *sc)
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return mwx_poll(sc, reg, WFSYS_SW_INIT_DONE, WFSYS_SW_INIT_DONE, 500);
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}
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/*
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* To be honest this is ridiculous.
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*/
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uint32_t
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mt7921_reg_addr(struct mwx_softc *sc, uint32_t reg)
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mwx_reg_addr(struct mwx_softc *sc, uint32_t reg)
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{
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static const struct {
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uint32_t phys;
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uint32_t mapped;
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uint32_t size;
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} fixed_map[] = {
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{ 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
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{ 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
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{ 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
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{ 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
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{ 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
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{ 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
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{ 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
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{ 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
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{ 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
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{ 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (conf register) */
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{ 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
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{ 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */
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{ 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */
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{ 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
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{ 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */
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{ 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
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{ 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
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{ 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
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{ 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
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{ 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
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{ 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
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{ 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
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{ 0x820cc000, 0x0e000, 0x01000 }, /* WF_UMAC_TOP (PP) */
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{ 0x820cd000, 0x0f000, 0x01000 }, /* WF_MDP_TOP */
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{ 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
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{ 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
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{ 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
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{ 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
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{ 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
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{ 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
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{ 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
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{ 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
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{ 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
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{ 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
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{ 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
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{ 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
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{ 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
|
||||
{ 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
|
||||
{ 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
|
||||
{ 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
|
||||
{ 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
|
||||
{ 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
|
||||
{ 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
|
||||
};
|
||||
int i;
|
||||
const struct mwx_connac_reg_map *map;
|
||||
size_t i, nelms;
|
||||
uint32_t low_limit;
|
||||
|
||||
if (reg < 0x100000)
|
||||
if (sc->sc_hwtype == MWX_HW_MT7925) {
|
||||
map = mt7925_fixed_map;
|
||||
nelms = nitems(mt7925_fixed_map);
|
||||
low_limit = 0x200000;
|
||||
} else {
|
||||
map = mt7921_fixed_map;
|
||||
nelms = nitems(mt7921_fixed_map);
|
||||
low_limit = 0x100000;
|
||||
}
|
||||
|
||||
if (reg < low_limit)
|
||||
return reg;
|
||||
|
||||
for (i = 0; i < nitems(fixed_map); i++) {
|
||||
uint32_t ofs;
|
||||
for (i = 0; i < nelms; i++) {
|
||||
uint32_t offset;
|
||||
|
||||
if (reg < fixed_map[i].phys)
|
||||
if (reg < map[i].phys)
|
||||
continue;
|
||||
|
||||
ofs = reg - fixed_map[i].phys;
|
||||
if (ofs > fixed_map[i].size)
|
||||
offset = reg - map[i].phys;
|
||||
if (offset > map[i].size)
|
||||
continue;
|
||||
|
||||
return fixed_map[i].mapped + ofs;
|
||||
return map[i].maps + offset;
|
||||
}
|
||||
|
||||
if ((reg >= 0x18000000 && reg < 0x18c00000) ||
|
||||
(reg >= 0x70000000 && reg < 0x78000000) ||
|
||||
(reg >= 0x7c000000 && reg < 0x7c400000))
|
||||
return mwx_map_reg_l1(sc, reg);
|
||||
(reg >= 0x7c000000 && reg < 0x7c400000)) {
|
||||
if (sc->sc_hwtype == MWX_HW_MT7925)
|
||||
return mt7925_map_reg_l1(sc, reg);
|
||||
else
|
||||
return mt7921_map_reg_l1(sc, reg);
|
||||
}
|
||||
|
||||
panic("%s: Access to currently unsupported address %08x\n",
|
||||
DEVNAME(sc), reg);
|
||||
|
||||
+14
-7
@@ -1,4 +1,4 @@
|
||||
/* $OpenBSD: if_mwxreg.h,v 1.10 2026/06/02 11:55:57 claudio Exp $ */
|
||||
/* $OpenBSD: if_mwxreg.h,v 1.11 2026/06/02 14:23:47 claudio Exp $ */
|
||||
/*
|
||||
* Copyright (c) 2022 Claudio Jeker <claudio@openbsd.org>
|
||||
* Copyright (C) 2021 MediaTek Inc.
|
||||
@@ -274,11 +274,18 @@
|
||||
#define MT_RX_FWDL_RING_BASE 0xd4500
|
||||
|
||||
#define MT_INFRA_CFG_BASE 0xfe000
|
||||
#define MT_HIF_REMAP_L1 0xfe24c
|
||||
#define MT_HIF_REMAP_L1_MASK 0x0000ffff
|
||||
#define MT_HIF_REMAP_L1_GET_OFFSET(x) ((x) & 0xffff)
|
||||
#define MT_HIF_REMAP_L1_GET_BASE(x) ((x >> 16) & 0xffff)
|
||||
#define MT_HIF_REMAP_BASE_L1 0x40000
|
||||
#define MT7921_HIF_REMAP_L1 0xfe24c
|
||||
#define MT7921_HIF_REMAP_L1_MASK 0x0000ffff
|
||||
#define MT7921_HIF_REMAP_L1_SHIFT 0
|
||||
#define MT7921_HIF_REMAP_BASE_L1 0x40000
|
||||
|
||||
#define MT7925_HIF_REMAP_L1 0x155024
|
||||
#define MT7925_HIF_REMAP_L1_MASK 0xffff0000
|
||||
#define MT7925_HIF_REMAP_L1_SHIFT 16
|
||||
#define MT7925_HIF_REMAP_BASE_L1 0x130000
|
||||
|
||||
#define MWX_HIF_REG_OFFSET(x) ((x) & 0xffff)
|
||||
#define MWX_HIF_REG_BASE(x) (((x) >> 16) & 0xffff)
|
||||
|
||||
#define MT_SWDEF_BASE 0x41f200
|
||||
#define MT_SWDEF_MODE 0x41f23c
|
||||
@@ -640,7 +647,7 @@ struct mt76_txwi {
|
||||
#define MT_TXD1_HDR_FORMAT_MASK 0x00030000
|
||||
#define MT_TXD1_HDR_FORMAT_SHIFT 16
|
||||
#define MT_TXD1_HDR_INFO_MASK 0x0000f800
|
||||
#define MT_TXD1_HDR_INFO(x) (((x) << 11) & MT_TXD1_HDR_INFO_MASK)
|
||||
#define MT_TXD1_HDR_INFO(x) (((x) << 11) & MT_TXD1_HDR_INFO_MASK)
|
||||
#define MT_TXD1_ETH_802_3 (1U << 15)
|
||||
#define MT_TXD1_VTA (1U << 10)
|
||||
#define MT_TXD1_WLAN_IDX_MASK 0x000003ff
|
||||
|
||||
Reference in New Issue
Block a user